The present invention relates to a semiconductor memory device, and more particularly to a phase correction circuit for correcting a phase of a clock signal of a semiconductor memory device to enhance operation reliability, and a phase correction method thereof.
In a system with a variety of semiconductor devices, a semiconductor memory device serves as a data storage. The semiconductor memory device outputs data corresponding to addresses received from a data processor, e.g., a central processing unit (CPU), or stores data received from the data processor into memory cells selected by addresses.
As the operating speed of the system increases and semiconductor integrated circuit technologies are advanced, semiconductor memory devices are required to input and output data at higher speed. To meet this requirement, a synchronous memory device was developed. The synchronous memory device is designed to input and output data in synchronization with a received system clock. However, since even the synchronous memory device could not meet the required data input/output speed, a double data rate (DDR) synchronous memory device was developed. The DDR synchronous memory device is designed to input or output data at falling edges and rising edges of the system clock.
The DDR synchronous memory device must process two data during one cycle of the system clock so as to input or output data at a falling edge and a rising edge of the system clock. In other words, the DDR synchronous memory device must output data or input/store data at the rising edge and the falling edge of the system clock. Specifically, the DDR memory device must output data exactly in synchronization with the rising edge or the falling edge of the clock.
To increase operating speed of the semiconductor memory device, a quad data rate (QDR) semiconductor memory device has been suggested. The QDR semiconductor memory device is designed to transfer four data during one cycle of the system clock. Seeing that the typical DDR semiconductor memory device can transfer two data during one cycle of the system clock, the QDR memory device can transfer up to two times more data than the typical semiconductor memory device in theory. The QDR memory device is different from the typical semiconductor memory device in that the QDR memory device uses two clocks, instead of using a single clock. One clock is used as a reference for transferring data, and the other clock is used as a reference for transferring addresses and commands for reading/writing the data, thereby increasing the speed of reading/writing data. The QDR memory device can be widely applied to high-speed telecommunication and network apparatuses where the speed of transferring data is more important than other factors such as power consumption, cost, and the like, and a graphic processing apparatus needing to read and write a large amount of data in a short time.
When a system clock is applied to such a semiconductor memory device, a clock input buffer and a transfer line for transferring the system clock may cause the system clock to be delayed and a phase of the system clock to be changed. To resolve this, the semiconductor memory device generally includes a phase correction circuit for correcting a phase of the system clock. The phase correction circuit may also be used to correct a phase of a reference clock for transferring data to the semiconductor memory device or to the outside. Specifically, the high-speed semiconductor memory device inputs/outputs data or addresses at both the rising edges and the falling edges of the reference clock. Therefore, a change in the phase of the reference clock may cause an insufficient margin to the overall operations of the semiconductor memory device, and thus failure or delay of operations.
The phase correction circuit detects a phase of a clock and then delays the clock by a delay time to correct the detected phase of the clock. If there is an error while detecting the phase, the error may decrease the accuracy of the correction operation of the phase correction circuit. Such an error may be increased as the semiconductor memory device is highly integrated and the operating speed of the semiconductor memory device is raised. Especially, as a line width of the circuit in the semiconductor memory device becomes finer, the error may be increased further. In addition, as a duty cycle of a clock received from the outside is decreased, an error ratio, i.e., the ratio of the error to the duty cycle of the clock, may be increased. The increase of the error ratio means that an operation margin of a read/write operation is decreased, or that an accurate operation cannot be performed in a predetermined duration. Therefore, operation reliability of the semiconductor memory device is decreased.
As described above, to allow the newly proposed QDR memory device to input/output four data during one cycle of the system clock, the data should be synchronized with phases of 0 degree, 90 degrees, 180 degrees, and 270 degrees of the system clock. In other words, the QDR memory device should output one data for each 90 degrees. As the data are synchronized exactly with the phases of the system clock, each data can have a maximum valid window for the operation of the semiconductor memory device, thereby enhancing the operation reliability of the semiconductor memory device. Therefore, whereas the typical semiconductor memory device has a phase correction circuit for maintaining a phase distance of 180 degrees between a rising edge and a falling edge, the QDR memory device needs a phase correction circuit for correcting a phase of an internal clock so that data is transferred exactly at the phases of 0 degree, 90 degrees, 180 degrees, and 270 degrees of the system clock.